Complementary metal oxide semiconductor (CMOS) nanosheet devices include a vertical stack of channel layers interconnecting a source and a drain. Advantageously, CMOS nanosheet devices can employ gate-all-around (GAA) designs since the channel layers are anchored at either end by the source and drain.
A drawback with current nanosheet device designs, however, is that the epitaxy growth process used to form the source and drains can cause parasitic growth on the underlying substrate. This parasitic growth can undesirably cause shorts between source and drain.
Thus, improved nanosheet device fabrication techniques would be desirable.